The present invention relates to logic elements for use with programmable logic devices or other similar devices.
Programmable logic devices (xe2x80x9cPLDsxe2x80x9d) (also sometimes referred to as CPLDs, PALs, PLAs, FPLAs, EPLDs, EEPLDs, LCAs, FPGAs, or by other names), are well-known integrated circuits that provide the advantages of fixed integrated circuits with the flexibility of custom integrated circuits. Such devices are well known in the art and typically provide an xe2x80x9coff the shelfxe2x80x9d device having at least a portion that can be electrically programmed to meet a user""s specific needs. Application specific integrated circuits (xe2x80x9cASICsxe2x80x9d) have traditionally been fixed integrated circuits, however, it is possible to provide an ASIC that has a portion or portions that are programmable; thus, it is possible for an integrated circuit device to have qualities of both an ASIC and a PLD. The term PLD as used herein will be considered broad enough to include such devices.
PLDs typically include blocks of logic elements, sometimes referred to as logic array blocks (xe2x80x9cLABsxe2x80x9d; also referred to by other names, e.g., xe2x80x9cconfigurable logic blocks,xe2x80x9d or xe2x80x9cCLBsxe2x80x9d). Logic elements (xe2x80x9cLEsxe2x80x9d, also referred to by other names, e.g., xe2x80x9clogic cellsxe2x80x9d) may include a look-up table (LUT) or product term, carry-out chain, register, and other elements.
Logic elements, including look-up table (LUT)-based logic elements, typically include configurable elements holding configuration data that determines the particular function or functions carried out by the logic element. A typical LUT circuit may include ram bits that hold data (a xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d). However, other types of configurable elements may be used. Some examples may include static or dynamic random access memory, electrically erasable read-only memory, flash, fuse, and anti-fuse programmable connections. The programming of configuration elements could also be implemented through mask programming during fabrication of the device. While mask programming may have disadvantages relative to some of the field programmable options already listed, it may be useful in certain high volume applications. For purposes herein, the generic term xe2x80x9cmemory elementxe2x80x9d will be used to refer to any programmable element that may be configured to determine functions implemented by a PLD.
A typical LUT circuit used as a logic element provides an output signal that is a function of multiple input signals. The particular logic function may be determined by programming the LUT""s memory elements. As will be explained further herein (see FIG. 1 and accompanying text), a typical LUT circuit may be represented as a plurality of memory elements coupled to a xe2x80x9ctreexe2x80x9d of 2:1 muxes. The LUT mux tree includes a first level comprising a single 2:1 mux providing the LUT output and also includes successive additional levels of muxes, each level including twice as many muxes as the previous level and the number of memory elements being twice as many as the number of 2:1 muxes in a last mux level coupled to the memory elements. Each 2:1 mux level provides a logic input to the LUT circuit coupled to control inputs of the muxes at that mux level. Thus, to obtain an n-input LUT (or xe2x80x9cnLUTxe2x80x9d) typically requires 2n memory elements and 2n muxes. Adding an input to an nLUT circuit to provide an n+1 input LUT (xe2x80x9c(n+1)LUTxe2x80x9d) therefore typically requires providing a total of 2n+1 memory elements and (2n+1xe2x88x921)muxes, i.e., approximately a doubling of resources relative to that required by an nLUT.
For many applications, the functions that need to be implemented by a first LUT circuit and a second LUT circuit are identical. Also, for some applications, it may be possible for inputs of first and second LUT circuits to be shared without reducing the functionality required by the application. In such instances, there are opportunities that need to be maximized for sharing resources to reduce the total number of memory elements and muxes that would otherwise be required.
In other instances, while also minimizing resources, it is useful to have the flexibility to switch between two nLUT circuits that maybe independently programmed to implement n-input functions and two (n+1)LUT circuits that can be programmed to implement the same n+1-input functions. It may also be desirable to, with minimal added resources, also have the added flexibility to select an additional option such as, for example, two LUT circuits that can implement at least some functions of n+2 inputs.
One embodiment of the present invention provides a shared-LUT logic circuit that provides the functionality of two (n+1)LUT logic circuits without requiring twice the resources of two nLUT circuits. Another embodiment of the present invention provides a shared-LUT logic circuit that may be configured to provide either the functionality of two nLUT circuits that may be independently programmed to provide n-input functions or the functionality of two (n+1)LUT circuits that may be programmed to provide the same n+1-input functions. Another embodiment of the present invention provides a shared-LUT logic circuit that may be configured to provide one of the following: (i) two nLUT circuits that may be programmed to provide independent n-input functions; (ii) two (n+1)LUT circuits that may be programmed to provide the same n+1-input functions; or (iii) two (n+2)LUT circuits that may be programmed to provide limited related n+2-input functions. In these and other illustrated embodiments, a plurality of muxes is interposed between an x and an x+1 mux level of first and second nLUT circuitry to implement sharing of at least some of the nLUT circuitry, thereby providing first and second (n+1)LUT circuits and variations thereon. In yet another embodiment, a plurality of muxes is interposed between a last mux level and memory elements of first and second nLUT circuitry to provide two (n+1)LUT circuits that do not require shared inputs and may be programmed to provide two independent n+1-input functions.